1. Field of the Invention
The present invention relates to a memory device, and more particularly, a Column Address Strobe (CAS) for a memory device.
2. Background of the Related Art
In general, DRAMs are a combination of capacitors and transistors, and are widely used as highly integrated semiconductor memories. However, because the operation of a DRAM is controlled by delaying command signals (RASB, CASB, and the like) and read of its data according to Y-address signal, the DRAM has the disadvantage that data reading time is long and slow. Consequently, recently developed Synchronous DRAMs (SDRAMs) have increased read and write speeds.
A related art CAS latency circuit for a SDRAM will be described with reference to the attached drawings. FIG. 1 illustrates a related art CAS latency control circuit for a SDRAM, FIG. 2 illustrates a system of the latching unit in FIG. 1, and FIG. 3 illustrates a system of the control inverter in FIG. 2.
Referring to FIG. 1, the related art CAS latency control circuit for a SDRAM is provided with three latches 2, 3, and 4, and a controlling circuit unit 1 for controlling the three latches 2, 3, and 4. Thus, controlling circuit unit 1 receives a clock signal QCLK for forwarding data, and provides control signals con1, con2, and con3 for controlling respective latches 2, 3, and 4.
First latch 2 either forwards or latches input data depending on the control signal con3 from the controlling circuit 1. Second latch 3 either forwards or latches the data from the first latch 2 according to the control signal con2 from the controlling circuit unit 1. Third latch 4 either forwards the data from the second latch 3 to an output buffer or latches the data from the second latch 3 according to the control signal con1 from the controlling circuit unit 1.
Referring to FIG. 2, each of the latches 2, 3, and 4 is provided with a first inverter 6 which inverts a control signal con3, con2, con1 from the controlling circuit unit 1. A first control inverter 5 passes data D when the control signal con1, con2, or con3 is "low" in response to the control signal con3, con2, or con1 and the signal from the first inverter 6. This is in the open condition of the latch. A second inverter 8 inverts a signal from the first control inverter 5, and a second control inverter 7 latches a data signal from the second inverter 8 when the control signal con1, con2, or con3 is "high" in response to the control signal con3, con2, or con1 and the signal from the first inverter 6.
Referring to FIG. 3, the control inverter 5 or 7 in each of the latches is provided with first and second PMOS transistors 9 and 10, and first and second NMOS transistors 11 and 12 between a constant supply voltage terminal and a ground voltage terminal. The second PMOS transistor 10 and the first NMOS transistor 11 receive a data signal D.sub.in at gates thereof, and the first PMOS 9 receives the control signal con3, con2, or con1 from the controlling circuit unit 1 or a signal from the first inverter 6 at a gate thereof. The second NMOS transistor 12 receives the control signal con3, con2, or con1 from the controlling circuit unit 1 or a signal from the first inverter 6 at a gate thereof, and an output terminal 13 is provided at a node of the second PMOS transistor 10 and the first NMOS transistor 11.
FIG. 4 illustrates a first timing diagram of the related art CAS latency control circuit operation, FIG. 5 illustrates a second timing diagram of the related art CAS latency control circuit operation, FIG. 6 illustrates a third timing diagram of the related art CAS latency control circuit operation, and FIG. 7 illustrates a fourth timing diagram of the related art CAS latency control circuit operation.
Referring to FIG. 4, the controlling circuit unit 1 provides control signals con1, con2, and con3 all at "low" at a first rising edge of a clock signal QCLK, so that all the latches 2, 3, and 4 do not latch data, but instead directly bypass the data. Therefore, the output data Dout is provided at a second rising edge of the clock signal QCLK.
Referring to FIG. 5, the controlling circuit unit 1 provides a control signal con1 to be applied to the third latch 4 at "high" and control signals con2 and con3 to be applied to the first and second latches 2 and 3 respectively at "low" at a first rising edge of a clock signal QCLK, so that the first and second latches do not latch the data. Instead, the data is passed directly to the third latch, which receives the data. Next, the controlling circuit unit 1 controls the control signal con1 to transition from "high" to "low" at a second rising edge of the clock signal, so that the data passes through the third latch 4 and proceeds toward the data output buffer. The controlling circuit unit 1 then transitions the control signal con1 from "low" to "high" again before a third rising edge of the clock signal, so that the data is latched at the third latch.
Referring to FIG. 6, the controlling circuit unit 1 holds the control signal con3 low and control signals con1 and con2 high in synchronization with the clock signal QCLK. It then transitions the control signal con1 from high to low after a second rising edge of the clock signal QCLK, and after a prescribed time period, from low to high again. The controlling circuit unit 1 causes the control signal con2 to transition from high to low when the control signal con1 transitions from low to high, and then from low to high at a third rising edge of the clock signal. Accordingly, the control signals con1 and con2 repeat the aforementioned process in a fourth rising edge of the clock signal. As the control signal is held low, the data passes through the first latch 2 to the second latch 3, and passes through the second latch 3 to the third latch 4 when the control signal con2 transitions to low.
In this instance, as the control signal con2 transitions to high again, the second latch 3 latches and holds the data provided to the third latch 4 until the control signal con2 is transited to low, again. And, when the control signal con1 is transited to low in a second cycle, the third latch 4 forwards the data toward the data output buffer, and when the control signal con1 is transited to high again, latches the data until the control signal con1 is transited to low and holds the data until the next cycle.
Referring to FIG. 7, the controlling circuit unit 1 maintains all of the control signals con1, con2, and con3 at a high level until a second rising edge of the external clock signal QCLK, when the control signals con1, con2, and con3 are transited to low in sequence. Therefore, when a pertinent signal transitions to low, the first latch 2 provides the latched data to the second latch 3, the second latch 3 provides to the third latch 4, and the third latch 4 provides to the data output buffer. Alternatively, when a pertinent control signal transitions from low to high, the data is latched. Thus, as data is provided depending on a user's selection of a mode of the first to fourth CAS latencies, the SDRAM operates faster than a general DRAM.
However, the related art CAS latency control circuit for a SRAM has various problems. For example, passing data through all the series connected latches, regardless of the cases of CAS latency, results in an unnecessary data transmission delay. Particularly, as the data passes directly through the first, second, and third latches without being latched by any of the latches, as in the case of the first CAS latency, e.g., FIG. 4, or latched only by the third latch as in the case of second CAS latency, e.g., FIG. 5, data transmission delay becomes a problem.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.